1. Field of the Invention
The present invention relates generally to serializer/deserializer circuitry (SerDes or SERDES) and related methods of data transmission. More particularly, the invention relates to a deserializer adapted for use within SerDes and having reduced data latency.
2. Description of Related Art
The term “SerDes” refers to a broad class of transceiver equipment and related methods of operation commonly used to transmit/receive data via high-speed serial links. In addition to other data communication systems, SerDes is being widely employed within semiconductor integrated circuit based system communicating higher bandwidth data. As part of its general functionality, SerDes routinely converts signal formed by parallel arrangements of data bits (i.e., “parallel signals”) to/from signals formed by serial arrangements of data bits (i.e., “serial signals”). As such, SerDes typically includes a serializer and a deserializer. Generally speaking, a serializer is a device configured to convert a parallel signal into a serial signal, and a deserializer is a device configured to convert a serial signal into a parallel signal.
Figure (FIG.) 1 is a block diagram of a data system incorporating SerDes. Referring to FIG. 1, data system 1 generally comprises SerDes 10, link layer 20 (e.g., an Application Specific Integrated Circuit or ASIC), and a host 30. Host 30 and link layer 20 are connected through SerDes 10 to facilitate the communication of large volumes of data (i.e., high bandwidth data).
SerDes 10 comprises a deserializer 100 and a serializer 200. Deserializer 100 receives serial data at a relatively high rate (i.e., “high-frequency data” or SDATA) from host 30, converts the high-frequency serial data into N-bit wide parallel data, where N is an integer greater than one, and then transfers the N-bit parallel data to link layer 20. In contrast, serializer 200 receives N-bit parallel data from link layer 20, converts it into high-frequency serial data, and then transfers the high-frequency serial data to host 30. In one conventional example, serializer 200 may be used to serialize 10-bit parallel data encoded using an 8B10B protocol and received from link layer 20.
FIG. 2 is a block diagram further illustrating deserializer 100 of FIG. 1. Referring to FIG. 2, deserializer 100 includes a parallel converter 1000 and a data aligner 2000. Parallel converter 1000 generates (or “recovers”) preliminary N-bit parallel data RXD′ from received high-frequency serial data, as well as a clock signal associated with the high-frequency serial data. Data aligner 2000 then performs data alignment to generate N-bit parallel data RXD by detecting a so-called comma (K28.5) from the recovered parallel data. Here, data aligner 2000 includes a comma detector 2200 generating a comma detection signal CDET.
FIG. 3 further illustrates an exemplary data alignment approach operatively within deserializer 100 which assumes the recovery of 10-bit parallel data by parallel converter 1000. In the illustrated example, the detected comma is a 7 bit data value while unit data byte size is defined as 10 bits. As deserializer 100 temporally aligns bytes of data (and bits within each byte of data) to restore the N-bit parallel data RXD, comma detector 2200 operates to detect a comma by checking 7 bit wide data groups. This may be accomplished by shifting bit for bit through a first byte to a second byte, etc. Comma detector 2200 generates the detection signal CDET upon detecting a comma. Data aligner 2000 operates to properly align the restored N-bit parallel data RXD in response to the detection signal CDET.
Under the foregoing assumptions, it is generally preferred that a maximum delay time for the recovery of N-bit parallel data be no longer than 6 transmission words (e.g., 240 bits). This preference arises from certain conditions associated with FC-AL monitoring or state arbitration processes. In the illustrated example of FIGS. 1-3, a delay time for each transmission word is a function of the time required to serialize/deserialize data within SerDes 20. Thus, data latency or the period required to pass data through the serialize/deserialize process is a critical system performance parameter. Reduction of data latency while ensuring accurate data recovery within a data deserializer is a highly desirable design objective.